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1 standard products ut22vp10 universal rad pal tm data sheet november 2000 features q high speed universal rad pal - t pd : 15.5ns, 20ns, 25ns maximum - f max1 : 33mhz maximum external frequency - supported by industry-standard programmer - amorphous silicon anti-fuse q asynchronous and synchronous rad pal operation - synchronous preset - asynchronous reset q up to 22 input and 10 output drivers may be configured - cmos & ttl-compatible input and output levels - three-state output drivers q variable product terms, 8 to 16 per output q 10 user-programmable output macrocells - registered or combinatorial operation - output driver polarity control selectable - two feedback paths available q radiation-hardened process and design; total dose irradia- tion testing to mil-std-883, method 1019 - total dose: 1.0e6 rads(si) - upset threshold 50 mev-cm 2 /mg (min) - latchup immune(let>109 mev-cm 2 /mg) q qml q & v compliant q packaging options: - 24-pin 100-mil center dip (0.300 x 1.2) - 24-lead flatpack (.45 x .64) - 28-lead quad-flatpack (.45 x .45) q standard military drawing 5962-94754 available 13 macrocell 8 14 macrocell 10 15 macrocell 12 16 macrocell 14 17 macrocell 16 18 macrocell 16 19 macrocell 14 20 macrocell 12 21 macrocell 10 22 macrocell 8 23 11 10 9 8 7 6 5 4 3 2 1 reset preset cp figure 1. block diagram 12 programmable array logic (132 x 44) v ss 24 v dd
2 product description the ut22vp10 rad pal is a fuse programmable logic array device. the familiar sum-of-products (and-or) logic struc- ture is complemented with a programmable macrocell. the ut22vp10 is available in 24-pin dip, 24-lead flatpack, and 28-lead quad-flatpack package offerings providing up to 22 inputs and 10 outputs. amorphous silicon anti-fuse technology provides the programming of each output. the user specifies whether each of the potential outputs is registered or combina- torial. output polarity is also individually selected, allowing for greater flexibility for output configuration. a unique output en- able function allows the user to configure bidirectional i/o on an individual basis. the ut22vp10 architecture implements variable sum terms providing 8 to 16 product terms to outputs. this feature provides the user with increased logic function flexibility. other features include common synchronous preset and asynchronous reset. these features eliminate the need for performing the initializa- tion function. the ut22vp10 provides a device with the flexibility to imple- ment logic functions in the 500 to 800 gate complexity. the flexible architecture supports the implementation of logic func- tions requiring up to 21 inputs and only a single output or down to 12 inputs and 10 outputs. development and programming support for the ut22vp10 is provided by data i/o. dip & flatpack pin configuration quad-flatpack pin configuration pin names function description the ut22vp10 rad pal implements logic functions as sum- of-products expressions in a one-time programmable-and/ fixed-or logic array. user-defined functions are created by programming the connections of input signals into the array. user-configurable output structures in the form of i/o macro- cells further increase logic flexibility. ck/i i i i i i i i i i i v ss v dd i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 i/o8 i/o9 i 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 ck/i clock/data input i data input i/o data input/output v dd power v ss ground 5 6 7 8 9 11 10 12 13 14 15 16 17 18 24 23 22 21 20 19 25 1 2 3 4 28 27 26 i i i v ss i i i i/o2 i/o3 i/o4 v ss i/o5 i/o7 i/o6 v dd ck/i i i v dd i/o0 i/o1 v ss i i i i/o9 i/o8 v ss
3 table 1. macrocell configuration table 1, 2, 3 overview the ut22vp10 rad pal architecture (see figure 1) has 12 ded- icated inputs and 10 i/os to provide up to 22 inputs and 10 outputs for creating logic functions. at the core of the device is a one-time programmable anti-fuse and array that drives a fixed or array. with this structure, the ut22vp10 can imple- ment up to 10 sum-of-products logic expressions. associated with each of the 10 or functions is a macrocell which is independently programmed to one of six different con- figurations. the one-time programmable macro cells allow each i/o to create sequential or combinatorial logic functions with either active-high or active-low polarity. logic array the one-time programmable and array of the ut22vp10 rad pal is formed by input lines intersecting product terms. the input lines and product terms are used as follows: 44 input lines: ? 24 input lines carry the true and complement of the signals applied to the input pins ? 20 lines carry the true and complement values of feedback or input signals from the 10 i/os 132 product terms: ? 120 product terms (arranged in 2 groups of 8, 10, 12, 14, and 16) used to form logic sums ? 10 output enable terms (one for each i/o) ? 1 global synchronous preset term ? 1 global asynchronous reset term at each input-line/product-term intersection there is an anti- fuse cell which determines whether or not there is a logical connection at that intersection. a product term which is con- nected to both the true and complement of an input signal will always be logical zero, and thus will not effect the or function that it drives. when there are no connections on a product term a don?t care state exists and that term will always be a logical one. product terms the ut22vp10 provides 120 product terms that drive the 10 or functions. the 120 product terms connect to the outputs in two groups of 8, 10, 12, 14, and 16 to form logical sums. macrocell architecture the output macrocell provides complete control over the archi- tecture of each output. configuring each output independently permits users to tailor the configuration of the ut22vp10 to meet design requirements. each i/o macrocell (see figure 2) consists of a d flip-flop and two signal-select multiplexers. three configuration select bits controlling the multiplexers determine the configuration of each ut22vp10 macrocell (see table 1). the configuration se- lect bits determine output polarity, output type (registered or combinatorial) and input feedback type (registered or i/o). see figure 3 for equivalent circuits for the macrocell configurations. output functions the signal from the or array may be fed directly to the output pin (combinatorial function) or latched in the d flip-flop (reg- istered function). the d flip-flop latches data on the rising edge of the clock. when the synchronous preset term is satisfied, the q output of the d flip-flop output will be set logical one at the next rising edge of the clock input. satisfying the asynchronous clear term sets q logical zero, regardless of the clock state. if both terms are satisfied simultaneously, the clear will override the preset. c 2 c 1 c 0 output type polarity feedback 0 0 0 registered active low registered 0 0 1 registered active high registered x 1 0 combinatorial active low i/o x 1 1 combinatorial active high i/o 1 0 0 registered active low i/o 1 0 1 registered active high i/o notes: 1. 0 equals programmed low or programmed. 2. 1 equals programmed high or unprogrammed. 3. x equals don?t care.
4 output polarity each macrocell can be configured to implement active-high or active-low logic. programmable polarity eliminates the need for external inverters. output enable the output of each i/o macrocell can be enabled or disabled under the control a programmable output enable product term. the output signal is propagated to the i/o pin when the logical conditions programmed on the output enable term are satisfied. otherwise, the output buffer is driven to the high-impedance state. the output enable term allows the i/o pin to function as a ded- icated input, dedicated output, or bidirectional i/o. when every connection is unprogrammed, the output enable product term permanently enables the output buffer and yields a dedicated output. if every connection is programmed, the enable term is logically low and the i/o functions as a dedicated input. register feedback the feedback signal to the and array is taken from the q output when the i/o macrocell implements a registered function (c 2 = 0, c 1 = 0). bidirectional i/o the feedback signal is taken from the i/o pin when the macro- cell implements a combinatorial function (c 1 = 1) or a regis- tered function (c 2 = 1, c 1 = 0). in this case, the pin can be used as a dedicated input, a dedicated output, or a bidirectional i/o. power-on reset to ease system initialization, all d flip-flops will power-up to a reset condition and the q output will be low. the actual output of the ut22vp10 will depend on the programmed output po- larity. the reset delay time is 5 m s maximum. see the power-up reset section for a more descriptive list of por requirements. anti-fuse security the ut22vp10 provides a security bit that prevents unautho- rized reading or copying of designs programmed into the de- vice. the security bit is set by the pld programmer at the con- clusion of the programming cycle. once the security bit is set it is no longer possible to verify (read) or program the ut22vp10. note: utmc does not recommend using the ut22vp10 unless the security fuse has been programmed. the security bit must be blown to ensure proper function- ality of the ut22vp10. c 1 c 0 ar c 2 sp d q ck q c 1 c 0 output select mux input/ feedback mux figure 2. macrocell c 1 c 2
5 registered feedback, registered, active-low output (c 2 = 0, c 1 = 0, c 0 = 0) ar sp d q ck q ar sp d q ck q registered feedback, registered, active-high output (c 2 = 0, c 1 = 0, c 0 = 1) i/o feedback, combinatorial, active-low output (c 2 = x, c 1 = 1, c 0 = 0) figure 3. macrocell configuration (continued on next page)
6 i/o feedback, combinatorial, active-high output (c 2 = x, c 1 = 1, c 0 = 1) ar sp d q ck q i/o feedback, registered, active-low output (c 2 = 1, c 1 = 0, c 0 = 0) ar sp d q ck q i/o feedback, registered, active-high output (c 2 = 1, c 1 = 0, c 0 = 1) figure 3. macrocell configuration
7 absolute maximum ratings 1 notes: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, fun ctional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. exposure to abso lute maximum rating conditions for extended periods may affect device reliability. 2. minimum voltage is -0.6v dd which may undershoot to -2.0v dd for pulses of less than 20ns. maximum output pin voltage is v dd +0.75v dd which may overshoot to +7.0v dd for pulses of less than 20ns. 3. (i cc max + i os ) 5.5v. recommended operating conditions notes: 1. see page 12 for minimum v dd requirements at power-up. symbol parameter limit units v dd supply voltage -0.3 to 7.0 v v i/o 2 input voltage any pin -0.3 to +7.0 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c t s lead temperature (soldering 10 seconds) +300 c q jc thermal resistance junction to case 20 c/w i i dc input current 10 ma p d 3 maximum power dissipation 1.6 w i o output sink current 12 ma symbol parameter limit units v dd 1 supply voltage 4.5 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 c
8 dc electrical characteristics 1, 7 (v dd 2 = 5.0v 10%; v ss = 0v 3, -55 c < t c < +125 c) notes: 1. all specifications valid for radiation dose < 1e6 rads(si). 2. see page 12 for minimum v dd requirements at power-up. 3. maximum allowable relative shift equals 50mv. 4. duration not to exceed 1 second, one output at a time. 5. tested initially and after any design or process changes that affect that parameter and, therefore, shall be guaranteed to the l imit specified. 6. all pins not being tested are to be open. 7. cmos levels only tested on cmos devices. ttl levels only tested on ttl devices. symbol parameter condition minimum maximum unit v il low-level input voltage ttl -- .8 v v ih high-level input voltage ttl 2.2 -- v v il low-level input voltage cmos -- .3*v dd v v ih high-level input voltage cmos .7*v dd -- v v ol low-level output voltage i ol = 12.0ma, v dd = 4.5v (ttl) .4 v v oh high-level output voltage i oh = -12.0ma, v dd = 4.5v (ttl) 2.4 -- v v ol low-level output voltage i ol = 200 m m a, v dd = 4.5v (cmos) -- v ss +0.05 v v oh high-level output voltage i oh = -200 m m a, v dd = 4.5v (cmos) v dd -0.05 -- v i in input leakage current v in = v dd and v ss -10 10 m a i oz three-state output leakage current v o = v dd and v ss , v dd = 5.5v -10 10 m a i os 4,5 short-circuit output cur- rent v dd = 5.5v, v o = v dd v dd = 5.5v, v o = 0v -160 160 ma c in 5,6 input capacitance | | =1mhz @0v -- 15 pf c i/o 5,6 bidirectional capacitance | | =1mhz @0v -- 15 pf i dd 5 supply current: output three-state, worst-case pat- tern programmed, | | =f max1 v dd = 5.5v -- 120 ma i ddq supply current: unprogrammed v dd = 5.5v -- 25 ma
9 ac characteristics read cycle (post-radiation) 1,2 (v dd 3 = 5.0v 10%; -55 c < t c < +125 c ) notes: 1. post-radiation performance guaranteed at 25 c per mil-std-883 method 1019 at 1.0e6 rads(si). 2. guaranteed by characterization. 3. see page 12 for minimum v dd requirements for power-up. 4. tested initially and after any design or process changes that affect. 5. device 22vp10-15 tested at -55 c, +25 c and +50 c. at 125 c, tested to 20ns limit. 6. tested on programmed test ring only. symbol parameter 22vp10-15.5 min max 22vp10-20 min max 22vp10-25 min max unit t pd 4,5,6 input to output propagation delay 15.5 20 25 ns t ea 4 input to output enable delay 23 23 25 ns t er 4 input to output disable delay 23 23 25 ns t co 4,6 clock to output delay 15 15 15 ns t co2 4 clock to combinatorial output delay via internal registered feedback 24 24 28 ns t s 4,6 input or feedback setup time 15 15 18 ns t h 4,6 input or feedback hold time 2 2 2 ns t p 4 external clock period (t co + t s ) 30 30 33 ns t wh, wl 4 clock width, clock high time, clock low time 12 12 14 ns f max1 4,6 external maximum frequency (1/(t co + t s )) 33 33 30 mhz f max2 4,6 data path maximum frequency (1/(t wh + t wl )) 42 42 36 mhz f max3 4,6 internal feedback maximum frequency (1/(t co + t cf )) 32 32 32 mhz t cf 4 register clock to feedback input 13 13 13 ns t aw 4 asynchronous reset width 20 20 25 ns t ar 4 asynchronous reset recovery time 20 20 25 ns t ap 4 input to asynchronous reset 20 20 25 ns t spr 4,6 synchronous preset recovery time 20 20 25 ns t pr 4,6 power up reset time 1.0 1.0 1.0 m s
10 v t t pd v t v t t s t h v t v t t co input or bidirectional input combinational output combinatorial output input or bidirectional input registered output clock registered output v t t wh t wl clock width v t input or bidirectional input output combinatorial output (v oh - 0.5v, v ol + 0.5v) v t t ea t er v t t ap t ar input asserting asynchronous reset v t v t clock registered output t aw v t v t v t clock registered output input asserting synchronous preset t s t h t spr v t t co asynchronous reset synchronous preset notes: 1. v t = 1.5v. 2. input pulse amplitude 0v to 3.0v. 3. input rise and fall times 3ns maximum. figure 4. ac electrical 1,2,3 t p
11 q q q clk clk f max3 ; internal feedback output register register q q clk clock to combinatorial output (t co2 ) output register product terms figure 5. signal paths d product terms d product terms product terms t cf 1 note: 1. t cf defined as the propagation delay from q to d register input. 1 t co + t cf d
12 power-up reset the power-up reset feature ensures that all flip-flops will be reset to low after the device has been powered up. the output state will depend on the programmed pattern. this feature is valuable in simplifying state machine initialization. see figure 6 for a timing diagram. due to the synchronous operation of the power-up reset and the wide range of ways v dd can rise to its steady state, the following five conditions are required to ensure a valid power-up reset. 1. the voltage supplied to the v dd pin(s) must be equal to 0v prior to the intended power-up sequence. 2. the voltage on v dd must rise from 0v to 1v at a rate of 0.1v/s or faster. 3. the v dd rise must be continuously increasing with respect to time, through 3v, and monotonic thereafter. 4. following reset, the clock input must not be driven from low to high until all applicable input and feedback setup times are met. 5. the power-up voltage must meet the minimum v dd require- ments described by the following device dependent and tem- perature dependent equations: radiation hardness the ut22vp10 rad pal incorporates special design and layout features which allow operation in high-level radiation environments. utmc has developed special low-temperature processing techniques designed to enhance the total-dose radiation hardness of both the gate oxide and the field oxide while maintaining the circuit density and reliability. for transient radiation hardness and l atchup immunity, utmc builds radiation-hardened products on epitaxial wafers using an advanced twin-tub cmos process. radiation hardness design specifications 1 note: 1. the rad pal will not latchup during radiation exposure under recommended operating conditions. smd device types 01, 02, 03, 04, 08 cmos and ttl v dd =4.61v -0.0090*( o c) smd device types 05, 06, 07 cmos v dd =4.41 -0.0090* ( o c) note: the minimum v dd requirement above is not applicable if the ut22vp10 application is purely combinatorial (i.e. no registered outputs). v dd registered active-low output clock v dd t wl v dd min t pr t s figure 6. power-up reset waveform parameter condition minimum unit total dose +25 c per mil-std-883 method 1019 1.0e6 rads(si) let threshold -55 c to +125 c 50 mev-cm 2 /mg neutron fluence 1mev equivalent 1.0e14 n/cm 2
13 figure 7. 24-pin 100-mil center dip (0.300 x 1.2) b 0.018 0.002 c 0.010 + 0 .002 - 0.001 top view side view front view detail a (no scale) lead ceramic body 0.040 max. braze fillet 0.025 max. 4 see detail a ea 0.300 0.010 a 0.166 0.110 b2 0.050 typ. l 0.200 0.125 l1 0.150 min. s1 0.005 min. typ. s2 0.005 min. -c- 4 q 0.060 0.015 0.010 c m 1 . 1 0 0 e 0 . 1 0 0 2 pin 1 index geometry opt. 23 24 d 1 . 2 0 0 0 . 0 1 5 0.50 r. (at seating plane) 12 11 13 14 24-ld 6038 5 e 0.295 0.010 0.310 0.010 notes: 1. package material: opaque ceramic. 2. all exposed metalized areas are finished per mil-prf-38535. 3. letter designations are for cross-reference to mil-std-1835. 4. for solder coated leads, increase maximum limit by 0.003 inch as measured at the center of the flat. 5. numbering and lettering on the ceramic are not subject to visual marking criteria.
14 figure 8. 24-lead flatpack (0.45 x 0.64) notes: 1. all exposed metalized areas are gold plated over electroplated nickel per mil-prf-38535. 2. the lid is electrically connected to v ss . 3. lead finishes are in accordance with mil-prf-38535. 4. dimension letters refer to mil-std-1835. 5. lead position and coplanarity are not measured. 6. id mark symbol is vendor option. 7. for solder coated leads, increase maximum limit by 0.003 inch as measured at the center of the flat. -b- 28 places h a-b d 5 s s 0.010 m pin no. 1 id. 6 5 -d- k 0.015 0.008 k 0.015 0.008 e 26 places 0.05 -a- s1 4 places 0.000 min. c 0.006 0.004 7 5 0.040 -h- e3 0.030 min. typ. e2 0.180 min. 0.420 0.350 -c- a 0.115 0.045 b 0.022 0.015 e1 0.450 max. q 0.045 0.026 l 0.370 typ. 0.250 0 . 6 4 0 m a x . h a-b d 0.036 m s s d 7
15 figure 9. 28-lead quad-flatpack (.45 x .45) notes: 1. all exposed metalized areas are gold plated over electroplated nickel per mil-prf-38535. 2. lead finishes are in accordance with mil-prf-38535. 3. dimension letters refer to mil-std-1835. 4. lead position and coplanarity are not measured. 5. mark is not subject to visual marking criteria. 6. mark is on lid and its symbol is vendor option. 7. for solder coated leads, increase maximum limit by 0.003 inch as measured at the center of the flat. c 0.008 0.001 top view side view view a-a -c- a a 0.040 package part number 5 0.980 sq. ref. see detail a. pin 1 id 0.250 min. typ. d o.450 0.007 sq. 1 28 -a- a 0.100 max. e 0.050 4 b 0.018 0.002 a1 0.065 0.007 c a b m m 0.030 m c 0.009 m 4 - b - e 0 . 4 5 0 r e f . 7050 detail a pin 1 id square corners. this pad only. back side pin 1 id mark
16 ordering information ut22vp10 radiation hardened pal: smd lead finish: (a) = solder (c) = gold (x) = optional case outline: (l) = 24-lead dip (x) = 24-lead pin flatpack (y) = 28-lead pin quad flatpack class designator: (q) = class q (v) = class v device type (01) = 25ns prop delay, cmos i/o (02) = 25ns prop delay, ttl i/o (03) = 20ns prop delay, cmos i/o (04) = 20ns prop delay, ttl i/o (05) = 25ns prop delay, cmos i/o (06) = 20ns prop delay, cmos i/o (07) = 15.5ns prop delay, cmos i/o (08) = 15.5ns prop delay, ttl i/o drawing number: 94754 total dose: (h) = 1e6 rads(si) (g) = 5e5 rads(si) (f) = 3e5 rads(si) (r) = 1e5 rads(si) federal stock class designator: no options 5962 * 94754 * * * * notes: 1. lead finish (a, c, or x) must be specified. 2. if an ?x? is specified when ordering, part marking will match the lead finish and will be either ?a? (solder) or ?c? (gold). 3. total dose radiation must be specified when ordering. qml q and qml v not available without radiation hardening. 4. (01-04, 08) is v dd (min) = -0.009*( o c)+4.61. 5. (05-07) is v dd (min) = -0.009*( o c)+4.41. 6. (07, 08) is tested at -55 c, + 25 c, and + 50 c to 15.5ns for t pd . at +1 25 c tested to 20ns limit for t pd .
17 ut22vp10 radiation hardened pal radiation: - = none lead finish: (a) = solder (c) = gold (x) = optional screening: (c) = military temperature (p) = prototype package type: (p) = 24-pin dip (u) = 24-pin flatpack (w) = 28-pin quad flatpack device type modifier: c-20 = cmos i/o: 20ns propagation delay c-25 = cmos i/o: 25ns propagation delay e-15 = cmos i/o: 15.5ns propagation delay e-20 = cmos i/o: 20ns propagation delay e-25 = cmos i/o: 25ns propagation delay t-15 = ttl i/o: 15.5ns propagation delay t-20 = ttl i/o: 20ns propagation delay t-25 = ttl i/o: 25ns propagation delay ut22vp10 * * * * * notes: 1. lead finish (a, c, or x) must be specified. 2. if an ?x? is specified when ordering, part marking will match the lead finish and will be either ?a? (solder) or ?c? (gold). 3. military temperature range flow per utmc?s manufacturing flows document. devices have 48 hours of burn-in and are tested at - 55 c , room temperature, and 125 c . radiation characteristics are neither tested nor guaranteed and may not be specified. 4. prototype flow per utmc manufacturing flows technical description. devices have prototype assembly and are tested at 25 c only. radiation is neither tested nor guaranteed. 5. (t-15, c-25, t-25, c-20, t-20) is v dd (min) = -0.009*( o c)+4.61. 6. (e-15, e-20 and e-25) is v dd (min) = -0.009*( o c)+4.41. 7. (e-15 and t-15) is tested at at -55 c, + 25 c, and + 50 c to 15.5ns for t pd . at +1 25 c tested to 20ns limit for t pd .
18 notes
19 notes

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